1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more specifically, to an electrically erasable programmable read only memory including cells each having a so-called "single polysilicon layer structure" in which a diffusion layer serving as a word line is formed in a substrate.
2. Description of the Related Art
FIG. 1 is a plan view of a pattern of an electrically erasable programmable read only memory (to be called EEPROM hereinafter) including cells each having a conventional "single polysilicon layer structure". FIG. 2 is a cross section of the EEPROM along the line I--I in FIG. 1. As can be seen in FIGS. 1 and 2, an N-type diffusion region 12 serving as a word line WL is formed in a P-type silicon substrate 10. A gate oxidation film 14 is formed on the diffusion region 12, and a polysilicon floating gate 16 is formed on the gate oxidation film 14. The floating gate 16 extends from a region above the diffusion region 12, over a region above a channel region 22. The channel region 22 is interposed between an N-type diffusion region 18 serving as a source of the cell transistor, and an N-type diffusion region 20 serving as a drain thereof. The diffusion region 18 is electrically connected to an aluminum alloy grounding wire 24 which is grounded (GND). Data is stored in accordance with a charge status of the floating gate. Specifically, data is determined depending on whether or not an inversion layer is formed in the channel region 22. For example, in the case where an inversion layer is formed in the channel region 22, the diffusion regions 18 and 20 are electrically connected to each other, and the potential of the diffusion layer 20 will be at the ground level. Then, when a selection gate (SG) 26 is set at the "H" level, an inversion layer is formed in the channel 30 located between the diffusion region 20 and an N-type diffusion region 28. The diffusion region 28 is also set at the ground level. Since the diffusion region 28 is electrically connected to an aluminum alloy bit line (BL) 32, the potential of the bit line 32 is also set at the ground level. In the case where no inversion layer is formed in the channel 22, the potential of the bit line 32 never varies. A field oxidation film 34 separates the diffusion region 12 serving as a word line and a cell transistor region from each other. An interlayer insulation film 36 insulates the polysilicon layer including the floating gate 16 and the selection gate 26, and the aluminum alloy layer including the grounding line 24 and the bit line 32 from each other. A tunnel oxidation film 38 injects electrons from the diffusion region 20 to the floating gate 16. A PSG film 40 and a silicon nitride film 42 are formed as the last passivation film consecutively on the grounding line 24 and the bit line 32. In the case of an EEPROM having the above-described single polysilicon layer structure, the silicon nitride film 42, once formed, can shut off the route which may carry contaminants including movable ions, moisture, etc., into the cell from outside.
However, before the formation of the nitride film 42, the route which may introduce these contaminants into the cell is not completely shut off, and therefore 10 the cell may be contaminated by these substances during the manufacturing procedure, degrading the reliability of the cell.